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Highly wireable multilevel synthesis with compiled cells
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In: Logic-and-Architecture-Synthesis-for-Silicon-Compilers.-Proceedings-of-the-International-Workshop ; https://hal.archives-ouvertes.fr/hal-00015340 ; Logic-and-Architecture-Synthesis-for-Silicon-Compilers.-Proceedings-of-the-International-Workshop, 1989, Grenoble, France. pp.37-52 (1989)
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| 2 |
A channelless layout for multilevel synthesis with compiled cells
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In: Proceedings.-1989-IEEE-International-Conference-on-Computer-Design:-VLSI-in-Computers-and-Processors-Cat.-No.89CH2794-6 ; https://hal.archives-ouvertes.fr/hal-00015347 ; Proceedings.-1989-IEEE-International-Conference-on-Computer-Design:-VLSI-in-Computers-and-Processors-Cat.-No.89CH2794-6, 1989, Cambridge, MA, United States. pp.35-8, ⟨10.1109/ICCD.1989.63323⟩ (1989)
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