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Compiler-Driven Simulation of Reconfigurable Hardware Accelerators ...
Abstract: As customized accelerator design has become increasingly popular to keep up with the demand for high performance computing, it poses challenges for modern simulator design to adapt to such a large variety of accelerators. Existing simulators tend to two extremes: low-level and general approaches, such as RTL simulation, that can model any hardware but require substantial effort and long execution times; and higher-level application-specific models that can be much faster and easier to use but require one-off engineering effort. This work proposes a compiler-driven simulation workflow that can model configurable hardware accelerator. The key idea is to separate structure representation from simulation by developing an intermediate language that can flexibly represent a wide variety of hardware constructs. We design the Event Queue (EQueue) dialect of MLIR, a dialect that can model arbitrary hardware accelerators with explicit data movement and distributed event-based control; we also implement a generic ...
Keyword: FOS Computer and information sciences; Hardware Architecture cs.AR; Machine Learning cs.LG; Programming Languages cs.PL
URL: https://dx.doi.org/10.48550/arxiv.2202.00739
https://arxiv.org/abs/2202.00739
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