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1
Strengthening Homeland Security through Improved Foreign Language Capability
In: DTIC (2011)
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2
Special Operations Forces Language and Culture Needs Assessment: Defense Language Proficiency Test (DLPT)
In: DTIC (2010)
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3
Relevance Feedback based on Constrained Clustering: FDU at TREC 09
In: DTIC (2009)
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4
BIT at TREC 2009 Faceted Blog Distillation Task
In: DTIC (2009)
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5
POSTECH at TREC 2009 Blog Track: Top Stories Identification
In: DTIC (2009)
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6
PRIS at 2009 Relevance Feedback track: Experiments in Language Model for Relevance Feedback
In: DTIC (2009)
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7
Minimum Bayes-Risk Decoding for Statistical Machine Translation
In: DTIC (2004)
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8
The Pragmatics of Taking a Spoken Language System Out of the Laboratory
In: DTIC (2003)
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9
Uses of the Diagnostic Rhyme Test (English Version) for Predicting the Effects of Communicators' Linguistic Backgrounds on Voice Communications in English: An Exploratory Study
In: DTIC (2000)
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10
The Bible, Truth, and Multilingual OCR Evaluation
In: DTIC (1998)
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11
Experiments in Spoken Document Retrieval at CMU
In: DTIC (1997)
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12
Domain and Language Evaluation Results
In: DTIC (1993)
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13
AMAR: A Computational Model of Autosegmental Phonology
In: DTIC AND NTIS (1993)
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14
A Practical Methodology for the Evaluation of Spoken Language Systems
In: DTIC (1992)
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15
Subject-Based Evaluation Measures for Interactive Spoken Language Systems
In: DTIC (1992)
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16
VHDL and Waves Descriptions for a Pseudo-Random Pattern Generator
In: DTIC AND NTIS (1992)
Abstract: A VHDL model for a 32-bit linear feedback shift register is documented, along with a WAVES dataset that provides test vectors for it. The register operates with a leading-edge dual clock, an asynchronous reset, and control bits to enable shifting (to the right) and loading. Other inputs are a polynomial and a seed value; the output is a bit pattern. The feedback feature is controller by the polynomial. For each polynomial bit position with a value of '1', the value of the register corresponding to that is fed through feedback before being shifted. The WAVES dataset is used to generate input test vectors for the register, and to provide a utility to compare actual outputs to predicted outputs. There are three different architectures for the register: structural behavioral, and structural with multiple component instantiations produced by the VHDL generate statement. There are also two architectures for the test bench: one that uses the WAVES dataset, and one that produces input vectors internally. The WAVES test bench uses a built-in utility to check outputs from each of the three register architectures against each other, and the non-WAVES test bench does these checks internally.
Keyword: *PATTERN GENERATORS; *PSEUDO RANDOM SYSTEMS; *VHDL; *VHDL(VHSIC HARDWARE DESCIPTION LANGUAGE); ARCHITECTURE; BENCH TESTS; CLOCKS; COMPUTER SIMULATION; Computer Systems; CONTROL; FEEDBACK; LANGUAGE; LEADING EDGES; Linguistics; PATTERN MAKING; PE62204F; POLYNOMIALS; SELF CONTAINED; TEST EQUIPMENT; VLSI; WAVES; WAVES(WAVEFORM ANALYSIS SYSTEM); WUWL60964018
URL: http://www.dtic.mil/docs/citations/ADA247891
http://oai.dtic.mil/oai/oai?&verb=getRecord&metadataPrefix=html&identifier=ADA247891
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17
Robust Processing of Real-World Natural-Language Texts
In: DTIC AND NTIS (1991)
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18
The Semantic Analyzer.
In: DTIC AND NTIS (1991)
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19
Very High Speed Integrated Circuits (VHSIC) Hardware Description Language (VHDL) Syntax and Semantics Summary
In: DTIC AND NTIS (1991)
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20
Adaptive Natural Language Processing
In: DTIC AND NTIS (1991)
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